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PRODUCT SPECIFICATION
PE83511
Military Operating Temperature Range
Product Description
The PE83511 is a high-performance static CMOS prescaler with a fixed divide ratio of 2. Its operating frequency range is DC to 1500 MHz. The PE83511 operates on a nominal 3V supply and draws only 14mA. It is packaged in a small 8-lead plastic MSOP and is ideal for frequency scaling and clock generation solutions. The PE83511 is manufactured in Peregrine's patented Ultra-Thin Silicon (UTSi) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS.
DC - 1500MHz Low Power CMOS Divide-by-2 Prescaler
Features * DC to 1500 MHz operation * Fixed divide ratio of 2 * Low-power operation: 14mA typical @ 3.0 V * Ultra small package: 8-lead plastic MSOP
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
3.05 2.85
D
Q QB
DRIVER OUTPUT BUFFER
OUT ____ OUT Enable ____ OUT
OUTPUT BUFFER 8-lead MSOP 5.05 4.75
IN
PREAMP
CLK
Table 1. Electrical Specifications (ZS = ZL = 50 )
2.85V VDD 3.15 V; -55 C TA 125 C, unless otherwise specified
Parameter
Supply Voltage
Conditions
Minimum
2.85
Typical
3.0 7 14
Maximum
3.15 12 25 1500 +10 +10 +10
Units
V mA mA MHz dBm dBm dBm dBm
OUTB Disabled Supply Current OUTB Enabled Input Frequency (FIN) 100 MHz Fin 1200 MHz -55C TA 85C Input Power (PIN) 100 MHz Fin 1200 MHz 85C TA 125C 1200 MHz < Fin 1500 MHz -55C TA 85C Output Power DC < Fin 1500MHz DC -5 0 +5 +2
PEREGRINE SEMICONDUCTOR CORP. |
http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 6
PE83511
Product Specification
Figure 3. Pin Configuration
VDD IN N/C GND 1 2 8 7 GND OUT CTL OUTB
Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
Description

PE83511
3 4 6 5
Table 2. Pin Descriptions
Pin No.
1 2 3 4
Pin Name
VDD IN N/C GND
Power supply pin. Bypassing is required (eg 1000 pF & 100 pF). Input signal pin. Should be coupled with a capacitor (eg 1000 pF). No connection. This pin should be left open. Ground pin. Ground pattern on the board should be as wide as possible to reduce ground impedance. Inverted divided frequency output. This pin should be coupled with a capacitor (eg 1000 pF). Control pin. When grounded OUTB is enabled. Divided frequency output. This pin should be coupled with a capacitor (eg 1000 pF). Ground Pin.
Device Functional Considerations The PE83511 divides an input signal, up to a frequency of 1500 MHz, by a factor of two thereby producing an output frequency at half the input frequency. To work properly at higher frequency, the input and output signals (pins 2 , 7 & optional 5) must be AC coupled via an external capacitor. The input may be DC coupled for low frequency operation with care taken to remain within the specified DC input range for the device. The ground pattern on the board should be made as wide as possible to minimize ground impedance. See Figure 7 for a layout example. OUTB Control Pin 6 controls weather OUTB is enabled or disabled. Pin 6 has an internal pull-up resistor. With no connection (floating), OUTB is disabled. By grounding pin 6, OUTB is enabled. By enabling OUTB, this part will consume roughly 5 mA more current.
5
OUTB
6 7
CTL OUT
8
GND
Table 3. Absolute Maximum Ratings
Symbol
VDD Pin VIN TST TOP VESD
Parameter/Conditions
Supply voltage Input Power Voltage on input Storage temperature range Operating temperature range ESD voltage (Human Body Model, MIL-STD 883)
Min
Max
4.0 15
Units
V dBm V C C V
-0.3 -65 -55
VDD +0.3 150 125 2000
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0113~02A
| UTSi CMOS RFIC SOLUTIONS
Page 2 of 6
PE83511
Product Specification
Typical Performance Data: VDD = 3.0V Figure 4. Input Sensitivity Figure 5. Device Current (OUTB Enabled)
Figure 6. Output Power (OUT or OUTB)
PEREGRINE SEMICONDUCTOR CORP. |
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Copyright Peregrine Semiconductor Corp. 2003
Page 3 of 6
PE83511
Product Specification
Figure 7. Evaluation Board Schematic Diagram
Figure 8. Evaluation Board Layout
J2-7
C10 10 pF
C2 1000 pF VDD GND
IN J1 C3 1000pF N/C
OUT
PE83511
CTL
C1 1000pF
J3
GND
OUT / C4 1000pF
J4
J5
Evaluation Kit Operation The PE83511 EK board was designed to ease customer evaluation of Peregrine's high performance divide-by-2 Military Grade Prescaler. On this board, the device input (pin 2) is connected via connector J1 and a 50 transmission line. A series capacitor (C3) provides the necessary DC block for the device input. It is important to note that the value of this capacitance will impact the performance of the device. A value of 1000 pF was found to be optimal for this board layout; other applications may require a different value. The device output (pin 7) is connected to connector J3 through a 50 transmission line. A series capacitor (C1) provides the necessary DC block for the device output. Note that this capacitor must be chosen to have low impedance at the desired output frequency the device. The value of 1000 pF was chosen to provide a wide operating range for the evaluation board. The board is constructed of a two-layer FR4 material with a total thickness of 0.031". The bottom layer provides ground for the RF
transmission lines. The transmission lines were designed using a coplanar waveguide above ground plane model with trace width of 0.030", trace gaps of 0.007", dielectric thickness of 0.028", metal thickness of 0.0014" and r of 4.4. Note that the predominate mode for these transmission lines is coplanar waveguide. J2 provides DC power to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device VDD pin (1). Two decoupling capacitors (10 pF, 1000 pF) are included on this trace. It is the responsibility of the customer to determine proper supply decoupling for their design application. Applications Support If you have a problem with your evaluation kit or if you have applications questions call (858) 455-0660 and ask for applications support. You may also contact us by fax or e-mail: Fax: (858) 455-0770 E-Mail: help@peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0113~02A
| UTSi CMOS RFIC SOLUTIONS
Page 4 of 6
PE83511
Product Specification
Figure 9. Package Drawing
8 Lead Plastic MSOP
TOP VIEW 0.65BSC 8 7 6 5 .525BSC
2.450.10 2X 3.000.10
0.510.13 -B1 2 3 4 .25 A B C
0.510.13
2.950.10
-C0.860.08 2.950.10
1.10 MAX -A0.10 A 0.33+0.07 -0.08 0.08 ABC 3.000.10 FRONT VIEW SIDE VIEW 0.100.05 3.000.10 4.900.15
Table 4. Ordering Information
Order Code
83511-01 83511-02 83511-00
Part Marking
PE83511 PE83511 PE83511-EK
Description
PE83511-08MSOP-50A PE83511-08MSOP-2000C PE83511-08MSOP-EK
Package
8-lead MSOP 8-lead MSOP Evaluation Kit
Shipping Method
50 units / Tube 2000 units / T&R 1 / Box
PEREGRINE SEMICONDUCTOR CORP. |
http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 5 of 6
PE83511
Product Specification
Sales Offices
United States
Peregrine Semiconductor Corp.
6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisiawaicho, Chiyoda-ku, Tokyo, Japan 100-011 Tel. 011-81-3-3502-5211 Fax. 011-81-3-3502-5213
Europe
Peregrine Semiconductor Europe
Aix-En-Provence Office Parc Club du Golf, bat 9 13856 Aix-En-Provence Cedex 3 France Tel 33-0-4-4239-3360 Fax 33-0-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice.
The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents are pending.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice).
Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright (c) 2002 Peregrine Semiconductor Corp. All rights reserved.
Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0113~02A
| UTSi CMOS RFIC SOLUTIONS
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